Design of an Energy Efficient CMOS Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects

Provided by: Institute of Electrical & Electronic Engineers
Topic: Mobility
Format: PDF
The Network-on-Chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing methods of implementing a NoC with planar metal interconnects are deficient due to high latency and significant power consumption arising out of multi-hop links used in data exchange. To address these problems, the authors propose design of a hierarchical small-world wireless NoC architecture where the multi-hop wire interconnects are replaced with high-bandwidth and single-hop long-range wireless shortcuts operating in the millimeter (mm)-wave frequency range. The proposed mm-wave Wireless NoC (mWNoC) outperforms the corresponding conventional wire-line counterpart in terms of achievable bandwidth and is significantly more energy efficient.

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