Design of Approximate Adder for Error Tolerant Application

Provided by: International Journal of Emerging Technology and Advanced Engineering (IJETAE)
Topic: Hardware
Format: PDF
The probability of errors in the present VLSI technology is very high and it is increasing with technology scaling. Removing all errors is very expensive task and is not required for certain applications. There are certain application where the approximate result is acceptable e.g. image processing and video processing. For these applications Error Tolerant Adder (ETA) is proposed which provide approximate result at very high speed than the convention adder. The proposed adder provides improvement in delay, power and area at the same time at the cost of accuracy.

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