Design of Area Efficient High Speed Parallel Multiplier Using Low Power Technique on 0.18um Technology
Based on the simplification of the addition operations in a low-power bypassing-based multiplier, a low-cost low-power bypassing-based multiplier is proposed. Row-bypassing multiplier, column-bypassing multiplier and Bruan multipliers are implemented in conventional method and GDI technique. By optimizing the transistor size in each stage the power and delay are minimized. The results of post-layout simulation compared to similar reported ones illustrate significant improvement. Simulation results show great improvement in terms of Power Delay Product (PDP). The experimental results show that the authors' proposed low-cost low-power multiplier saves hardware cost and reduces the power dissipation.