Design of Area Efficient Low Power CMOS Full Adder Using 32nm Technology

The 14T full adder cells proposed in this paper, utilizes low power by using pass transistor logic and transmission gate. The power consumption of 14T is reduced by decreasing the transistors count, about 50% compared with conventional full adder. The simulation results are carried out by using Microwind Lite based on 32 nm CMOS technology at 1.2 V supply voltages. The simulation results of 1-bit adder cell 14T full adder are compared with conventional full adder in terms of power consumption, area, time delay and power delay product parameters.

Provided by: Institute of Research and Journals (IRAJ) Topic: Hardware Date Added: Jul 2013 Format: PDF

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