Design of AXI Bus for 32-Bit Processor Using Bluespec

Provided by: International Journal of Advanced Research in Computer Engineering & Technology
Topic: Data Centers
Format: PDF
For high frequency on-chip communication architecture design, AXI bus is proposed. With the need of application and high performance, chip with a single processor can't meet the need of more and more complex computational task. The authors are able to integrate multiple processors on a chip, thanks to the development of integrated circuit manufacturing technology, 32 bit RISC processor which gives a solution to this requires efficient on-chip communication architectures to support high data bandwidth and increase parallelism. The traditional form of interconnection between multiple cores usually is on-chip bus (such as AHB and Avalon), which determiners the Performance of 32 bit RISC processor.

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