Design of Bypassing Multipier with Different Adders
Multiplication is one of the essential operations in Digital Signal Processing (DSP) applications like Fast Fourier Transform (FFT), digital filters, etc. Multiplier is designed, considering the tradeoffs between low power and high speed. The bypassing multiplier is an improvement, over Braun multiplier which is one of the parallel array multiplier. The tradeoffs i.e. dynamic power and delay of the bypassing multipliers can be reduced by using different adders. This paper presents a comparative study of 1-dimensional and 2-dimensional bypassing multipliers using different adders on basis of delay, area and power and for 4x4, 8x8 and 16x16-bits in FPGA Spartan-3E using Xilinx 12.4 ISE and Synopsys respectively.