Design of Compact Implementation of SHA-3(512) on FPGA
In this paper, the authors present a compact design of newly selected Secure Hash Algorithm (SHA-3) on Xilinx Field Programmable Gate Array (FPGA) device Spartan-3E. The design is logically optimized for area efficiency by merging rho, pi and chi steps of algorithm into single step. By logically merging these three steps they save 16% logical resources for overall implementation. It in turn reduced latency and enhanced maximum operating frequency of design. It utilizes only 240 slices and has frequency of 301.02MHz's comparing the results of their design with the previously reported FPGA implementations of SHA3-512, their design shows the best Throughput Per Slice (TPS) ratio of 30.1.