Reversible logic plays a very important role in recent times as reducing power consumption in digital logic design. Reversible logic contains a feature of recovering bit loss from unique input-output mapping where conventional logic has failed. Here, the reversible low power n-bit binary comparator has been designed. The two new reversible gates namely BJS and HLN gates are used to design an n-bit binary comparator. In addition, several theorems on the number of gates, garbage outputs, constant input, quantum cost, delay, power and area of n-bit binary comparator have been presented.