Design of Compressor Based Multiplier Using Degenerate Pass Transistor Logic

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Provided by: International Journal of Engineering Trends and Technology
Topic: Hardware
Format: PDF
In this paper, the authors propose a multiplier and compressors based on degenerate Pass Transistor Logic (PTL). Threshold loss problem are the main drawback in most pass transistor logic family. This threshold loss problem can be minimized by using the complementary control signals. These complementary control signals are obtained by 5-transistor XOR XNOR module. By using these complementary outputs, they designed parallel prefix adders based on 10-transistor full adder. Compressor is used to speed up the binary multiplication and these compressors are more flexible to perform multiplication of higher order bits in complex circuits.
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