Design of Digital FIR Filter Using LUT Based Multiplier
In FPGA design the implementation fir filters for DSP applications place an important role. The FPGA area is mainly decided by the number of LUT's occupied. Hence for any design if the optimization for the area is carried out for LUT's, then delay will also reduce. To optimize filters using LUT's for memory based multiplications, four basic techniques are used from which the combination of two techniques i.e., APC and OMS gave better optimization results. Further if Distributed Arithmetic (DA) technique is utilized for the filter design approach.