Design of Digital Phase Locked Loop for Wireless Communication Receiver Application

In this paper, frequency modulated receiver is designed using digital phase locked loop circuitry which consists of Booth s multiplier, loop filter and numerically controlled oscillator. This design is modelled in Verilog synthesis and performed place and route for design using Xilinx 13.1.In this paper, the authors propose a numerically controlled oscillator that can be tuned to desirable frequency according to the requirement. This design also achieves small area and small power consumption as compared to typical classical method of design.

Provided by: International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE) Topic: Enterprise Software Date Added: Aug 2015 Format: PDF

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