Design of Efficient Hardware Utilization Fault Coverage Circuit

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Provided by: The World
Topic: Hardware
Format: PDF
A new fault coverage test pattern generator using a Linear Feedback Shift Register (LFSR) called FC-LFSR can perform fault analysis and reduce the power of a circuit during test by generating three intermediate patterns between the random patterns by reducing the hardware utilization. The goal of having intermediate patterns is to reduce the transitional activities of Primary Inputs (PI) which eventually reduces the switching activities inside the Circuit Under Test (CUT) and hence power consumption is also reduced without any penalty in the hardware resources.
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