Design of Four Bit FLASH ADC using Clocked Digital Comparator

In this paper the authors describe the design of high speed flash ADC using clocked digital comparator with 4-bit resolution. The comparator is designed in an 180nm CMOS technology with supply voltage of 1.8 V. High speed clocked digital comparator with inverter configuration is used for dynamic offset suppression. As a result, a significant improvement of speed and reduction of area and power consumption is achieved. This paper describes the design of 4-bit flash ADC using multiplexer based decoder and clocking circuit.

Provided by: Creative Commons Topic: Hardware Date Added: Mar 2013 Format: PDF

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