Carnegie Mellon University
An on-chip interconnect is a critical shared resource that affects the performance-energy envelope of an entire multicore system. This aspect has led to a plethora of proposals in recent years for efficiently architecting the NoC substrate. However, most of these designs are agnostic to the actual application requirements in that they attempt to optimize a generic set of objective functions such as latency and throughput and/or energy/power. In this paper, the authors show that not all applications demand similar resources from the underlying interconnection substrate.