International Journal of Emerging Technology and Advanced Engineering (IJETAE)
Carry SeLect Adder (CSLA) is very fast adder in all other adder. Only carry select adder is the fastest adders which are used in many data-processing processors to perform fast arithmetic operation. From the design of the CSLA, it is clear that there is scope for reducing the area and delay in the CSLA. This paper uses very simple and efficient gate-level modification to reduce the area and delay of the CSLA. Based on this modification 8-bit, 16-bit and square-root CSLA architecture have been developed and it is compared with the regular SQRT CSLA architecture.