International journal of Engineering and Management Research (IJEMR)
SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. This paper has shown that realistic stages are limited to radix-2 and radix-4. Higher radix dividers are therefore formed by a combination of low-radix stages. In this paper, the authors present an analysis of the n-bit divider and comparative analysis of different dividers in case of delays and performance. They show the performance and area results for a wide variety of divider architectures and implementations.