Design of High Performance Single Precision Floating Point Multiplier

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Provided by: IT Society of India (ITSI)
Topic: Hardware
Format: PDF
The speed of an ALU depends greatly on the speed of its multipliers and adders. The proposed paper deals with the implementation of a high performance, single precision floating point multiplier using fast adders and fast multipliers. Compared to the 32-bit floating point multiplier which uses Wallace tree with Kogge-stone adder in the final stage for mantissa multiplication, the implemented 32-bit floating point multiplier uses Vedic multiplication for mantissa multiplication and was found to have 25% improvement in speed and 33% reduction in gate count, thereby reducing the total power consumption.
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