Design of High Performance Split Path Data Driven Dynamic Full Adders

Addition is a fundamental arithmetic operation which is used in different applications such as Digital Signal Processing (DSP) and microprocessors. Single bit adder is the main component of any arithmetic circuit. This paper presents the design of new split-path Data Driven Dynamic (sp-D3L) full adder circuit. Power consumption of proposed adder varies from 0.584nW to 2.914nW with variation in supply voltage from 1.8V to 3.3V. Maximum output delay shows variation from 57.18ps to 423.15ps with variation of supply voltage from 1.8V to 3.3V.

Provided by: Prannath Parnami Insititute of Management & Technology (PPIMT) Topic: Hardware Date Added: Dec 2013 Format: PDF

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