Design of High- speed FIR Filter Based on Booth Radix-8 Multiplier Implemented on FPGA
Finite Impulse Response (FIR) digital filters have potential for high-speed and low-power realization through parallel processing on FPGA. In this paper, an efficient implementation of FIR filters, which uses a Booth Radix-8 multiplier, is suggested. For implementation of the said FIR filter MATLAB FDATool is employed to determine various filter coefficients. The 8 order FIR filters have been designed using VHDL language. The proposed FIR filter is simulated and synthesized using Xilinx ISE 12.4i. FPGAs implementation results show that the proposed design filter has an improved speed in comparison to previous published results.