Design of High Speed -Low Power-High Accurate (HS-LP-HA) Adder

Provided by: International Association of Computer Science & Information Technology (IACSIT)
Topic: Networking
Format: PDF
In modern VLSI technology the speed and power would always be a trade off. In contrast to that the proposed design gives better technique in improving the speed of computation with high accuracy when compared with conventional adders. And also the implementation gives low power results with better performance. Using the available VLSI design techniques and emerging concepts the High Speed Low Power High Accurate (HS-LP-HA) Adder is proposed. The proposed HS-LP-HA adder is capable to give near accurate value along with much low power consumption when compared with conventional adder. Hence also improved power delay product.

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