Design of High Speed Low Power Reversible Vedic Multiplier and Reversible Divider

Provided by: International Journal of Engineering Research and Applications (IJERA)
Topic: Hardware
Format: PDF
In this paper, the authors bring out a 32x32 bit reversible Vedic multiplier using "Urdhva Tiryakabhayam" sutra meaning vertical and crosswise, is designed using reversible logic gates, which is the first of its kind. Also in this paper, they propose a new reversible unsigned division circuit. This circuit is designed using reversible components like reversible parallel adder, reversible left-shift register, reversible multiplexer and reversible n-bit register with parallel load line. The reversible Vedic multiplier and reversible divider modules have been written in Verilog HDL and then synthesized and simulated using Xilinx ISE 9.2i.

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