Design of High Speed Multiplier Using Vedic Mathematics Technique

Provided by: Creative Commons
Topic: Hardware
Format: PDF
Now-a-days, everybody wants high speed processor which may take less time for execution. Due to its high speed processing ability, a multiplier is needed. The mostly occurring problems in a multiplier are power dissipation and more delay. So the authors use Vedic multiplier which results in minimum delay. They are using 4x4 bit Vedic Multiplier which consists vertical and crosswise algorithm. This process has been seem to be large optimization of speed. They made this paper with the help of Xilinx software.

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