Design of High Speed Reconfigurable Coprocessor for Multiplier/Adder and Subtractions Operations

Provided by: IOSR Journal of Engineering
Topic: Data Centers
Format: PDF
As the quantity of data transmission and reception increases, there is a gradual increase in bandwidth on demand and quality of service. This further increases data traffic which leads to loss of information, reduced accuracy and reliability. To overcome this drawback, the authors proposed coprocessor can be used for communication operations, such as scrambling, interleaving, convolutional encoding, viterbi decoding, FFT, and several other functions using the proposed design. The coprocessor has been modeled by VHDL. Performance comparisons shows that the number of clock cycles can be reduced about 48% for scrambling and 84% for convolutional encoding compared with existing DSPs.

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