Provided by: Academy & Industry Research Collaboration Center
In this paper, the authors present three different approaches which eliminate the resistor ladder completely and hence reduce the power demand drastically of an Analog to Digital Converter (ADC). The first approach is Switched Inverter Scheme (SIS) ADC; the test result obtained for it on 45nm technology indicates an offset error of 0.014LSB. The full scale error is of -0.112LSB. The gain error is of 0.07LSB, actual full scale range of 0.49V, worst case DNL and INL each of -0.3V.