Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)

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Provided by: Institute of Electrical and Electronics Engineers
Topic: Hardware
Format: PDF
Because of its high storage density with superior scalability, low integration cost and reasonably high access speed, Spin-Torque Transfer Random Access Memory (STT RAM) appears to have a promising potential to replace SRAM as last-level on-chip cache (e.g., L2 or L3 cache) for microprocessors. Due to unique operational characteristics of its storage device Magnetic Tunneling Junction (MTJ), STT RAM is inherently subject to write latency versus read latency tradeoff that is determined by the memory cell size. This paper first quantitatively studies how different memory cell sizing may impact the overall computing system performance, and shows that different computing workloads may have conflicting expectations on memory cell sizing.
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