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The logical effort model is mainly to reduce delay in a circuit, but does not show how to minimize power and area. This paper deals with an empirical modeling and design of logical effort for estimating power in CMOS logic gates. The power is estimated in a circuit using the power of standard inverter and the relationship established between Power (P) and logical effort (g), electrical effort (h) and Parasitic (P) have been proposed in this paper. To verify the above model a full adder circuitry producing just the carry-out in UMC 90nm CMOS technology having supply voltage of 1V is selected.