Institute of Electrical and Electronics Engineers
In this paper, the authors propose an area-efficient (Fast Fourier Transform) FFT processor for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable lengths of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with Mixed-Radix (MR) and Multi-path Delay Commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in Hardware Description Language (HDL) and implemented with Xilinx Virtex-4 FPGA.