Design of Low Power 16-Bit Novel Carry Select Adder using 0.18um Technology

In this paper, a novel 16-bit Carry SeLect Adder (CSLA) is proposed to perform fast arithmetic operation in many data-processing processors. The proposed design combines the modified 16-bit carry select adder and a carry select adder by sharing the common Boolean Logic term. The area and power of the novel 16-bit carry select adder significantly reduces when compared with modified 16-bit carry select adder. This paper evaluates the performance of the proposed design in terms of total number of gates, area, delay and power using Cadence Virtuoso gpdk 180nm technology.
Provided by: International Journal of Computer Applications Topic: Hardware Date Added: Jan 2015 Format: PDF

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