Design of Low Power 4-Bit CMOS Braun Multiplier Based on Threshold Voltage Techniques

A circuit design for a new low power 4-bit Braun multiplier is presented. The multiplier is implemented by using different threshold voltage techniques. Power reduction techniques are proposed for 4-bit Braun multiplier which is designed by full adders. To get optimum design low threshold voltages are used at critical paths similar way high threshold voltages are used at non-critical paths. The design uses CMOS digital circuits in order to reduce the power dissipation while maintaining computational throughput. This architecture is simulated at 90nm technology with 1.2v power supply.

Provided by: Global Journals Topic: Hardware Date Added: Jan 2015 Format: PDF

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