Design of Low Power and High Speed Components of SAR ADC
Main building blocks of a SAR-ADC are: sample & hold circuit, comparator, timing and logic control which is mainly SAR logic, DAC (Digital to Analog Converter) in the feedback loop of ADC. For low-power applications designer needs to come up with a compromise among speed and resolution. In this paper, the components for SAR ADC are designed in 0.18 um CMOS technology in such a way that the total power is minimized. CMOS has been the dominant technology for VLSI implementation. As VLSI circuits continue to grow and technologies evolve, the level of integration is increased and higher clock speeds are achieved.