Design of Low Power and High Speed Error Tolerant Adder Cells for Digital Signal Processing Applications

In the modern VLSI systems, with the technology reaching below 45nm, it is impossible to avoid errors and simultaneously a trade-off between power and speed has become an important design consideration. With huge datasets, this requirement becomes even more stringent. To meet the needs, the systems must be made error-tolerant. In this paper, the authors standardize the error-tolerant adder and compare its performance with the existing adder cells. The given ETA cell is better than other adder cells in terms of power, delay and PDP values.