Design of Low Power Asynchronous 6 Transistor SRAM in 45nm CMOS with the Use of Pass Transistor Based Tree Decoders and Static CMOS Based Timing Circuitry Along with Process Variation Simulation
In this paper, the authors describe the design of a 6 Transistor Static Random Access Memory (6T SRAM) in 45nM CMOS along with the design of the peripheral components such as the pass transistor based tree decoders and static CMOS based timing circuit. The basic memory-cell is simulated for read and write-margin variations with a 10% variation in threshold voltage and the complete system design is simulated using test patterns of repetitive 1s and0s. At a clock frequency of 250MHz, the design consumes 28.6fJ/bit.
Provided by: Institute of Research and Journals (IRAJ) Topic: Hardware Date Added: Jan 2014 Format: PDF