Design of Low Power Bypassing-Based Multiplier Using VHDL

In this paper, a low power bypassing -based multiplier design is present, in which reduction in power is to be achieved in changed partial products of column bypassing multiplier as compared to column bypassing multiplier by exchange NOR gates with AND gates in the conventional multiplier i.e. in the design of conventional multiplier rather than AND gate, NOR gate is employed victimization DeMorgan's theorem. Compare with 32×32 bits typical (parallel array) multiplier and column bypassing multiplier, this planned system reduces power.

Provided by: Iosrjournals Topic: Hardware Date Added: Jun 2014 Format: PDF

Find By Topic