Design of Low Power Carry Look-Ahead Adder Using Single Phase Clocked Quasi-Static Adiabatic Logic
Efficiency of adiabatic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. Lesser be the losses more energy efficient would be the circuit. In this paper, a new approach i.e., Complementary Energy Path Adiabatic Logic (CEPAL), is presented to minimize power dissipation in Quasi Static Energy Recovery Logic (QSERL). It optimizes circuit, by avoiding non-adiabatic losses completely by replacing the diodes with MOSFETs. MOSFET gates are controlled by power clocks and this is implemented in carry look-ahead adder structure.