Design of Low Power Counters Using Reversible Logic

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Provided by: International Journal of Innovative Research in Science, Engineering and Technology (IJIRSET)
Topic: Hardware
Format: PDF
In today's world, the complexity of the chip is increasing as more and more devices are being connected on a single chip. Due to the high density of the chip, the power dissipation increases demanding better power optimization methods. One of the methods to achieve power optimization is by using reversible logic. It can be used in low power CMOS designs, quantum computing, nanotechnology and optical computing. This paper presents an optimized sixteen-bit binary sequential counter based on reversible logic using Feynman and Fredkin gates.
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