International journal of Engineering and Management Research (IJEMR)
Reversible logic is an emerging research area. Interest in this field is motivated by its applications in several technologies involving low voltages and low power. Binary reversible circuits have been studied for their potential application in low-power CMOS design, quantum computation, nanotechnology, optical computation, etc. In this paper, a Reversible low power Decoder is proposed; circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented.