Design of Low Power Half Adder Using Adaptive Voltage Level (AVL) Technique

Provided by: International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE)
Topic: Hardware
Format: PDF
In VLSI arithmetic circuits plays an important role. In this adder is one of the arithmetic circuits. In this paper, the half adder is being designed by using Adaptive Voltage Level (AVL) techniques. These designs are used to reduce the power consumption compared to other conventional design. The authors can reduce the value of the total power dissipation by using Adaptive Voltage Level at Ground (AVLG) technology in which the ground potential is raised to reduce power consumption and Adaptive Voltage Level at Supply (AVLS) in which the supply potential is increased to reduce the power consumption.

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