Design of Low Power High Speed Fully Dynamic CMOS Latched Comparator

A novel of low power high speed comparator is proposed in this paper, which consists of less sensitive in delay using dynamic CMOS latched comparator method. It aimed for less sensitive in delay and high speed design compared with other design techniques. The simulation results carried out using LT spice tool shows up to 62% less sensitivity of the delay, which is about 0.098ns than the conventional double-tail latched comparators at approximately the same area and power consumption.

Provided by: International Journal of Engineering Research and Development (IJERD) Topic: Hardware Date Added: Apr 2014 Format: PDF

Find By Topic