Design of Low Power Multipliers Using Approximate Adder

Provided by: International Journal of Pure and Applied Research in Engineering and Technology (IJPRET)
Topic: Hardware
Format: PDF
Power consumption is a major issue for circuit design in CMOS technology. In most multimedia applications, human eyes can gather useful information from slightly imprecise outputs. To reduce power consumption for applications in which strict exactness is not required, approximate implementations of a circuit have been considered as a potential solution. In imprecise computing, power reduction is achieved through the relaxation of accuracy. Previous research on logic complexity reduction has focused on gate, algorithm and logic levels.

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