Design of Low Power Negative Pulse-Triggered Flip-Flop with Enhanced Latch

In this paper, a new low power pulse-triggered flip-flop is designed with enhanced latch where the pulse-generation circuit is constructed using one pmos transistor and data is transferred through two nmos transistors and a inverter, when compared with the conventional pulse-triggered flip-flops, it consumes only 0.373µw of power to activate the circuit and occupies only less area on chip i.e. 5 transistors and two inverters. The simulation results are done based on CMOS 50nm technology.

Provided by: Iosrjournals Topic: Hardware Date Added: Oct 2013 Format: PDF

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