Design of Low Power Optimized Filter Architecture Using VLSI Technique

Provided by: International Journal of Innovative Technology and Exploring Engineering (IJITEE)
Topic: Hardware
Format: PDF
In the prevalence of DSP applications the weighted operations are the multiplication and accumulation. Multiplier-ACcumulator (MAC) unit that consumes low power is always a means to accomplish a high concert digital signal processing system. Finite Impulse Response (FIR) filters are widely used in various DSP applications where signal were present with noise (e.g. data converters). Uptill many proficient techniques have been introduced for the design of low snag bit-parallel Multiple Constant Multiplications (MCM) process which reduces the intricacy of many digital signal processing systems.

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