Design of Low Power Phase Frequency Detectors for Delay Locked Loop

Provided by: International Journal of Emerging Science and Engineering (IJESE)
Topic: Hardware
Format: PDF
A dynamic de-skew circuit can be used to ensure good clock alignment across variations in Process, Voltage and Temperature (PVT). The DLL is such a circuit, using a first-order closed-loop architecture that dynamically aligns its output clock signal with a reference clock signal. A simple new Phase Frequency Detector design is presented in this paper. The PFD which helps Delay Locked Loop (DLL) to achieve simultaneous phase and frequency error detection is an indispensable block and plays an important role in improving the performance of the whole DLL system.

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