Design of Low Power Pipelined ADC
Pipelined Analog-to-Digital Converters (ADC) architecture has gained great popularity in data communication and video processing applications where high sampling rates and medium-to-high resolutions are necessary due to the increasing demand for portability in these applications, reducing the power consumption of ADC has become one of the key design criteria. A design of 8 bits, 2.5V pipeline ADC is introduced in this paper. The comparator is the main improvement aiming at realizing low power dissipation. The latched comparator is adopted to achieve the specification. The design is implemented under 0.25um CMOS technology which achieves a power dissipation of 205.9mW.