Design of Low Power Scalable Digital CMOS Comparator Using a Parallel Prefix Tree

Provided by: IRD India
Topic: Hardware
Format: PDF
In this paper, the authors propose a comparator design using conventional digital CMOS cells featuring wide-range and high-speed operation. The comparison is most basic arithmetic operation that determines whether one number is greater than, less than or equal to the other number. Their comparator uses a novel scalable parallel prefix structure that leverages the comparison outcome of the MSB, proceeding bitwise towards LSB only when the comparison bits are equal. This comparator is composed of locally interconnected CMOS gates with a maximum fan-in of five and fan-out of four, independent of comparator bandwidth. Comparator is most fundamental component that performs comparison operation.

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