Design of Low Power Vedic Multiplier Using Adaptive Hold Logic

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Provided by: International Journal of Emerging Technology in Computer Science and Electronics ( IJETCSE)
Topic: Hardware
Format: PDF
Now-a-days, the growth of portable devices is increasing prominently. So, the designers need to limit the high power consumption in the devices. Digital multiplication is most commonly used in the arithmetic operations in many applications like digital signal processing, discrete cosine transform and in various scientific arithmetic circuits. Overall performance of the VLSI system is mainly depends on the multiplier. Furthermore, the negative bias temperature instability effects when pMOS transistors are stressed under negative bias. As a result, it leads to threshold voltage is increase and also multiplier speed is reducing. Positive bias temperature instability occurs, when nMOS transistors are stressed under positive bias.
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