Design of LRSM Algorithm for Multiplications of Large Numbers

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Provided by: International Journal of Engineering Innovations and Research (IJEIR)
Topic: Hardware
Format: PDF
The design of high-speed, area-efficient and low power multiplier is essential for the VLSI implementation of DSP systems. In many applications, like digital filtering, the inputs are contaminated by noise and precise outputs are often not required. A new high precision serial multiplier with most significant digit first is presented. This method uses a borrow save adder to perform the reduction of large length partial products required by the multiplications of large numbers. The results are converted from Borrow-Save (BS) form to 2's complement representation by the on the fly conversion which let the conversion of the digit result as soon as it is obtained.
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