Design of Multi Bit LFSR Pnrg and Performance Comparison on FPGA Using VHDL
The main purpose of this paper is to study the FPGA implementation and performance analysis of 8, 16, and32 bit LFSR pseudo random number generator system. The authors have used FPGA to explain how FPGA's ease the hardware implementation part of communication systems. The analysis is conceded out to find number of gates, memory and speed requirement in FPGA as the number of bits is increased. The comparative study of 8, 16 and 32 bit LFSR on FPGA is shown here to understand the on chip verification. Recently the field programmable gate arrays have enjoyed wide spread use due to several advantages related to relatively high gate density, short design cycle and low cost.