Design of Noise Tolerant Circuits for Modified Feedthrough Logic

Provided by: World Academic Industry Research Collaboration Organization (WAIRCO)
Topic: Hardware
Format: PDF
In this paper, a circuit design technique to improve noise tolerant of a new CMOS domino logic family called feedthrough logic is presented. The feedthrough logic improves the performance of arithmetic circuit as compared to static CMOS and domino logic but its noise tolerant is very less. A 2-input NAND gate is designed by the proposed technique. The ANTE (Average Noise Threshold Energy) metric is used for the comparison of noise tolerance of proposed circuit with the feedthrough logic.

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