Provided by: Creative Commons
Date Added: May 2014
In this paper, the authors investigate the implementation of a low power FIR filter using add and shift multiplier and carry save adder. This method is used to reduce the dynamic power consumption, delay and area of a low power FIR filter. This method include modified booth encoding algorithm combined with spurious power suppression technique, low power digital serial multiplier along with carry look ahead adder, shift and add multiplier. This proposed FIR filter was synthesized and implemented using Xilinx ISE V7.1 and also the power is analyzed using Xilinx X-power analyzer.