Provided by: Compusoft
Date Added: Apr 2014
In this paper, the authors propose a novel design of PT-PFD for low power and high speed PLL applications with an incredible phase noise and with a jitter performance. The proposed PT-PFD has been designed for high frequency PLL in 180nm CMOS Technology with 1.0v supply voltage. Functionality of the proposed design has been verified through simulations carried out using CADENCE Spectre tool. The proposed design uses only 6 transistors & the maximum high frequency operation is at 8GHz.